1. Field of the Invention
The present invention relates to a solid-state imaging apparatus and a manufacturing method thereof, and particularly to a solid-state imaging apparatus equipped with interlayer lenses and a manufacturing method thereof.
2. Description of the Related Art
In recent years, an amplifying type image sensor, such as a charge coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor, has been used for an image inputting apparatus, such as a digital camera, a video camera, and an image reader. At that time, as a higher performance solid-state imaging apparatus, the amplifying type image sensor including an increased number of photoelectric conversion elements by reducing the areas of the photoelectric conversion elements thereof performing photoelectric conversions and a further reduced chip size has been desired.
If the areas of the photoelectric conversion elements are reduced, then the quantity of receivable light lessens and the sensitivity of the image inputting apparatus lowers as the areas of the light receiving surfaces of the photoelectric conversion elements decrease. As a measure of the sensitivity lowering, the technique of forming on-chip micro lenses over the light receiving surfaces and condensing lights on the light receiving surfaces to suppress the fall of the sensitivity is known.
Japanese Patent Application Laid-Open No. 2004-186407 discloses the configuration of lessening the sizes from the on-chip micro lenses to the light receiving surfaces in their height directions in addition to the mounting of the on-chip micro lenses.
FIG. 7 shows the CMOS type solid-state imaging apparatus of Japanese Patent Application Laid-Open No. 2004-186407. An effective pixel region is arranged on the right side A of an alternate long and short dash line, in which effective pixel region a plurality of pixels is arranged. Each of the plurality of pixels includes a photoelectric conversion element performing a photoelectric conversion according to an incident light quantity. The region on the left side of the alternate long and short dash line is the region (hereinafter referred to as an out-of effective pixel region) other than the effective pixel region.
The CMOS type solid-state imaging apparatus includes photoelectric conversion regions 1, a first metal wiring 2, and a second metal wiring 3 as illustrated in FIG. 7. The on-chip micro lenses 5 are mounted over the first metal wiring 2 with a color filter 4 put between them. A step 6 is formed between the effective pixel region A and the out-of effective pixel region B. The second metal wiring 3, which is the uppermost wiring existing in the out-of effective pixel region B, does not exist in the effective pixel region A to lessen the distance h of the effective pixel region A from the light receiving surfaces in FIG. 7 (distance h<distance h′ in FIG. 7).
If the step 6 in the solid-state imaging apparatus of FIG. 7 disperses in a surface of the solid-state imaging apparatus or among different solid-state imaging apparatus, then the sensitivity of the solid-state imaging apparatus sometimes disperses. In order to suppress the dispersion of the sensitivity, it is important to manufacture the solid-state imaging apparatus so that the distances between the interlayer lenses and the photoelectric conversion elements may be uniform in the effective pixel regions A. However, Japanese Patent Application Laid-Open No. 2004-186407 did not sufficient examination of the manufacturing method of the solid-state imaging apparatus illustrated in FIG. 7. Moreover, in order to further improve the condensing efficiency into the photoelectric conversion regions 1, it is required to further lessen the distances between the lenses 5 and the photoelectric conversion elements (to realize a low profile).